In recent years, a nonvolatile memory device incorporating a memory cell configured to include a resistance variable element has been studied and developed. As used herein, the resistance variable element refers to an element which has a characteristic in which its resistance values change reversibly in response to electric signals and is capable of storing data corresponding to the resistance values in a nonvolatile manner.
The memory cell including the resistance variable element is configured in, for example, a cross-point structure. In the cross-point structure, memory cells are respectively arranged at cross points of bit lines and word lines which cross each other in a direction perpendicular to each other such that each memory cell is sandwiched between the associated bit line and the associated word line. A practicable area of the memory cell is 4F2. Patent literature 1 discloses a cross-point resistance variable memory device incorporating a bipolar resistance variable element. In this resistance variable memory device, when data is written, Vpp is applied to a selected bit line, Vss (0V) is applied to a selected word line, and 1/2Vpp is applied to an unselected word line and to an unselected bit line, while when data is erased, Vpp is applied to a selected word line, Vss (0V) is applied to a selected bit line, and Vpp/2 is applied to an unselected word line and to an unselected bit line.
As a nonvolatile memory device incorporating the resistance variable element, a nonvolatile memory device is generally known, in which 1T1R memory cells are arrayed in matrix at intersections of bit lines, word lines, and source lines, and the word lines and the source lines extending in a direction perpendicular to the bit lines, such that each memory cell includes a MOS transistor and a resistance variable element which are coupled to each other in series. A necessary area of the memory cell is 6F2 at least.
Patent literature 2 discloses a nonvolatile memory device including a 1T1R memory cell comprising oxide having a perovskite crystalline structure as a resistance variable element.
FIG. 47 is a schematic view of a cross-section of the memory cell disclosed in FIG. 2 of Patent literature 2.
A memory cell 1011 includes a transistor 1006 and a resistance variable element 1010 which are electrically connected to each other in series.
The transistor 1006 includes on a semiconductor substrate 1001, a source region 1002 which is a first diffusion layer region, a drain region 1003 which is a second diffusion layer region, and a gate electrode 1005 formed on a gate oxide layer 1004.
The resistance variable element 1010 includes a resistance variable layer 1008 which changes resistance values in response to voltages applied, a lower electrode 1007, and an upper electrode 1009 such that the resistance variable layer 1008 is sandwiched between the lower electrode 1007 and the upper electrode 1009.
The drain region 1003 is electrically connected to the lower electrode 1007.
The upper electrode 1009 is connected to a metal wire which serves as a bit line 1012, the gate electrode 1005 is connected to a word line, and the source region 1002 is connected to a metal wire which serves as a source line 1013.
As a material used for the resistance variable layer 1008, Pr1−xCaxMnO3, La1−xCaxMnO3 (LCMO) and other materials are disclosed, but an electrode material is not mentioned specifically.
A method of writing data to the memory cell 1011, is also disclosed, in which the resistance variable layer 1008 changes from a low-resistance state to a high-resistance state when Vpp is applied to the upper electrode 1009, Vss is applied to the source region 1002, and a pulse voltage with a specified voltage amplitude Vwp is applied to the gate electrode, while the resistance variable layer 1008 changes from the high-resistance state to the low-resistance state when Vss is applied to the upper electrode 1009, Vpp is applied to the source region 1002, and a pulse voltage with a specified voltage amplitude Vwe is applied to the gate electrode.
Patent literature 3 and Patent literature 4 disclose a structure for achieving an area of memory cell of 4F2 using the 1T1R memory structure.
FIG. 48 is a circuit diagram disclosed in FIG. 5 of Patent literature 3. As shown, a memory cell is configured to include a resistance variable element and a transistor which are arranged in parallel. A memory array is configured by connecting memory cells in series. With this arrangement, the area of the memory cell is determined by the area of the transistor and can be reduced to 4F2 in practice.